1. Field of the Invention
This invention relates to a voltage multiplier for stepping up a voltage, and more particularly to a voltage multiplier for use in a nonvolatile semiconductor memory.
2. Description of the related art
Recently, nonvolatile semiconductor memories which each have a floating gate and in which data can be electrically erased and programmed have been widely applied instead of the conventional ultraviolet erasable nonvolatile semiconductor memories. In such electrically erasable and programmable nonvolatile semiconductor memories, the data programming or erasing operation may be effected by injecting electrons into the floating gate via a thin oxide film of 100 .ANG. to 200 .ANG., for example, or emitting the electrons from the floating gate utilizing the Fouler-Nordheim tunneling effect. In the data programming or erasing operation, a high voltage of +10 to +20 V which is sufficiently higher than the normal power source voltage of +5 V is used. The current capacity of the high voltage can be set to be extremely small. Therefore, the high voltage is generally supplied from a voltage multiplier formed in the integrated circuit in which the memory is arranged so as to step up the power source voltage of +5 V. Formation of the voltage multiplier in the integrated circuit makes it possible to use only one power source voltage to be externally supplied to the integrated circuit, thus giving a great advantage to the user.
The prior art voltage multiplier is disclosed in the article by J. F. Dickson, "On-chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique", IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. SC-11, NO. 3, pp. 374 to 378, June 1986, for example.
FIG. 1 is circuit diagram showing the construction of the voltage multiplier which is modified so as to be suitably formed in the MOS integrated circuit. The source-drain paths of N-channel MOS transistors 71 are connected in series between power source voltage terminal Vcc and a node from which stepped-up voltage Vpp is derived. The gates of transistors 71 are connected to the respective sources thereof. Capacitors 72 are connected at one end to the respective gates of transistors 71. The other ends of those of capacitors 72 which lie in the odd stages are supplied with clock signal .phi.1 and the other ends of those capacitors which lie in the even stages are supplied with clock signal .phi.2. As shown by the timing chart of FIG. 2, clock signals .phi.1 and .phi.2 are generated such that the high level components will not occur in the same period.
In the voltage multiplier of the above construction, power source voltage Vcc of +5 V is sequentially stepped up in response to clock signals .phi.1 and .phi.2 to supply high voltage Vpp of +20 V, for example.
FIG. 3 is a circuit diagram showing the construction of a basic circuit of the conventional voltage multiplier. The basic circuit includes a first stage circuit formed of transistor 71A and capacitor 72A and a second stage circuit formed of transistor 71B and capacitor 72B. The conventional circuit of FIG. 1 can be obtained by connecting the basic circuits in cascade fashion. Approx. 10 basic circuits are necessary to constitute a circuit for deriving out high voltage Vpp of +20 V from power source voltage Vcc of +5 V.
Now, the operation of the basic circuit of FIG. 3 is explained with reference to the timing chart shown in FIG. 4. When clock signals .phi.1 and .phi.2 are both at "L" level, transistors 71A and 71B are both turned off. Therefore, the potentials of nodes 73 and 74 to which the drains of transistors 71A and 71B are connected are kept at previous potential levels V73 and V74.
When clock signals .phi.1 and .phi.2 are set at "H" and "L" levels, respectively, the potential of node 73 is stepped up by amplitude V.phi. of clock signal .phi.1 and set to (V73+V.phi.) by means of capacitor 72A. At this time, transistor 71A is turned on and node 74 is charged to (V73+V.phi.-Vth) via transistor 71A. In this case, Vth denotes the threshold voltage of transistor 71.
Next, when clock signals .phi.1 and .phi.2 are both set at "L" level again, transistors 71A and 71B are both turned off, and the potentials of nodes 73 and 74 are kept at the previous potential levels.
After this, when clock signals .phi.1 and .phi.2 are set at "L" and "H" levels, respectively, the potential of node 74 is stepped up by amplitude V.phi. of clock signal .phi.2 and set to (V74+V.phi.) by means of capacitor 72B. At this time, transistor 71A is turned off and transistor 71B is turned on, and therefore node 75 is charged to (V74+V.phi.-Vth) via transistor 71B.
Subsequently, the above operation is repeatedly effected and the potential is raised by 2(V.phi.-Vth) in each basic circuit, thus supplying desired high voltage Vpp from the final stage.
However, in the actual voltage multiplier, a current flows in a load when it is driven by the stepped-up voltage. As a result, as shown by the timing chart of FIG. 5, the potential of node 73 is raised by clock signal .phi.1 and then lowered by V.sub.L by a current flowing via transistor 71A which is set in the conductive state. Likewise, the potential of node 74 is raised by clock signal .phi.2 and then lowered by V.sub.L by a current flowing via transistor 71B which is set in the conductive state. In this way, the potential stepped up in each basic circuit of the actual circuit is 2(V.phi.-Vth-V.sub.L).
As described above, in the conventional voltage multiplier, since the potential raised in each basic circuit is lowered by the threshold voltage of the transistor, the amplitude of the clock signal or power source voltage Vcc must be set to be not less than +3V. That is, the potential raised by means of each basic circuit is 2(V.phi.-Vth-V.sub.L). Since the back gate effect becomes larger in the latter stage basic circuit, threshold voltage Vth of the transistor in the latter stage basic circuit generally becomes larger. In a case where an intrinsic type (I-type) transistor having the initial threshold voltage of 0 V is used as transistor 71, the threshold voltage will be 1 V in the worst case. Assume that V.sub.L is 1 V and voltage Vpp of +20 V is derived by using 10 basic circuits. Then, it is necessary to set the lowest level of V.phi. or Vcc to +3 V. In this case, if the number of the basic circuits is excessively increased, the voltage step-up efficiency may be lowered by a leak current or the like and approx. 10 may be the upper limit thereof. The chip area will be significantly increased with an increase in the number of the basic circuits.
As described above, the conventional voltage multiplier has a narrow operation power source voltage margin and is particularly disadvantageous in the low operation voltage. Further, since the voltage step-up efficiency in each basic circuit is low, it becomes necessary to arrange a number of basic circuits in order to derive a desired output voltage and therefore the chip area will be increased when the whole circuit is integrated.